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Integrated Circuit Systems, Inc.
ICS9150-08
Frequency Generator & Integrated Buffers for Pentium/ProTM
General Description
The ICS9150-08 generates all clocks required for high speed RISC or CISC microprocessor systems such as Intel PentiumPro or Cyrix. Eight different reference frequency multiplying factors are selectable. Features include three CPU, seven PCI and seventeen SDRAM clocks. Two reference output is available equal to the crystal frequency, plus two IOAPIC outputs powered by VDDL1. One 48 MHz for USB is provided plus a 24 MHz. Spread Spectrum built in at 0.5% or 0.25% modulation to reduce EMI. Serial programming I 2C interface allows changing functions, stop clock programing and Frequency selection. It is not recommended to use dual function I/O pins to clock slots (ISA, PIC, CPU, DIMM). The add on card may have a pull-up or pull-down. Additionally, the device meets the Pentium power-up stabilization, which requires that CPU and PCI clocks be stable within 2ms after power-up. High drive PCICLK and SDRAM outputs typically provide greater than 1 V/ns slew rate into 30pF loads. CPUCLK outputs typically provide better than 1V/ns slew rate into 20pF loads while maintaining 505% duty cycle. The REF, 24 and 48 MHz clock outputs typically provide better than 0.5V/ns slew rates into 20pF.
Features
3.3V outputs: SDRAM, PCI, REF, 48/24MHz 2.5V outputs: CPU, IOAPIC 20 ohm CPU clock output impedance 20 ohm PCI clock output impedance Skew from CPU (earlier) to PCI clock - 1 to 4 ns, center 2.6 ns. No external load cap for CL =18pF crystals 250 ps CPU, PCI clock skew 250ps (cycle to cycle) CPU jitter Smooth CPU frequency switching from 50 to 133 MHz I2C interface for programming 2ms power up clock stable time Clock duty cycle 45-55%. 56 pin 300 mil SSOP package 3.3V operation, 5V tolerant inputs (with series R) <5.5ns SDRAM propagation delay from Buffer Input
Block Diagram
Pin Configuration
Power Groups
VDD1 = REF (0:1), X1, X2 VDD2 = PCICLK_F, PCICLK(0:5) VDD3 = SDRAM (0:18), supply for PLL core, VDD4 = 48MHz, 24MHz VDDL1 = IOAPIC_F VDDL2 = CPUCLK_F (1:2)
9150-08 Rev E 09/28/98
56-Pin SSOP
* Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
Pentium is a trademark of Intel Corporation I2C is a trademark of Philips Corporation.
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
ICS9150-08
Pin Descriptions
PIN NUMBER 2 PIN NAME REF1 FS21 REF0 PCI_STOP# TYPE OUT IN OUT IN PWR IN OUT OUT IN OUT IN IN IN OUT IN OUT IN PWR DESCRIPTION 14.318 MHz reference clock output Latched frequency select input. Has pull-up to VDD2. 14.318MHz reference clock output Halts PCICLK (0:5) at logic "0" level when low. (in mobile, MODE=0) Ground. 14.318MHz input. Has internal load cap, (nominal 33pF). Crystal output. Has internal load cap (33pF) and feedback resistor to X1 Free running BUS clock not afected by PCI_STOP# Latched input for MODE select. Converts pin 3 to PCI_STOP# when low for power management. PCI Clock Outputs. Input for Buffers Serial data in for serial config port. (I2C) Clock input for serial config port. (I2C) 24MHz clock output for Super I/O or FD. Latched frequency select input. Has pull-up to VDD4. 48MHz clock output for USB. Latched frequency select input. Has pull-up to VDD2. Nominal 3.3V power supply, see power groups for function.
3
4, 10, 23, 26, 34, 42, GND 48, 53 5 6 8 9, 11, 12, 13, 14, 16 17 27 28 30 FS01 29 1, 7, 15, 20, 31, 37, 45 18, 19, 21, 22, 24, 25, 32, 33, 35, 36, 38, 39, 40 41, 43, 44, 46 47 50, 56 55 51, 49 52 54 48MHz FS11 VDD2, VDD1, VDD3, VDD4 SDRAM (1:8) (15:12) (7:0), 16 CPU_STOP# VDDL2, VDDL1 IOAPIC0 CPUCLK (1:2) CPUCLK_F IOAPIC_F X1 X2 PCICLK_F MODE1 PCICLK (0:5) BUFFERIN SDATA SCLK 24MHz
OUT
SDRAM clocks Halts CPUCLK (1:2), IOAPIC0, SDRAM (0:16) clocks at logic "0" level when low. CPU and IOAPIC clock buffer power supply, either 2.5 or 3.3V nominal. IOAPIC clock output. (14.318 MHz) Poweredby VDDL1 CPU Output clocks. Powered by VDDL2 (60 or 66.6MHz) Free running CPU output clock. Not affected ty the CPU_STOP#. Freerunning IOAPIC clock output. Not affected by the CPU_STOP# (14.31818 MHz) Powered by VDDL1
IN PWR OUT OUT OUT OUT
Notes: 1: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to program logic Hi to VDD or GND for logic low.
2
ICS9150-08
Mode Pin - Power Management Input Control
MODE, Pin 8 (Latched Input) 0 1 Pin 3 PCI_STOP# (INPUT) Ref 0 (OUTPUT)
Power Management Functionality
CPU_STOP# PCI_STOP# CPUCLK Outputs Stopped Low Running Running Stopped Low PCICLK (0:5) Running Running Stopped Low Stopped Low PCICLK_F, REF, 24/48MHz and SDRAM Running Running Running Running Crystal OSC Running Running Running Running VCO
0 1 1 0
1 1 0 0
Running Running Running Running
VDD1,2,3 = 3.3V5%, VDDL1,2 = 2.5V5% or 3.35%, TA=0 to 70C Crystal (X1, X2) = 14.31818MHz
FS2 1 1 1 1 0 0 0 0 FS1 1 1 0 0 1 1 0 0 FS0 1 0 1 0 1 0 1 0 CPU (M H z) 100.2 133.3 1 112 1 103 6 6 .8 8 3 .3 75 50 P C IC LK (M H z) 33.3 (C PU/3) 33.3 (C PU/4)1 37.3 1 34.3 (C PU/3) 33.4 (C PU/2) 41.65 (C PU/2) 37.5 (C PU/2) 25 (C PU/2) R EF, IO A P IC (M H z) 1 4 .3 1 8 1 4 .3 1 8 1 4 .3 1 8 1 4 .3 1 8 1 4 .3 1 8 1 4 .3 1 8 1 4 .3 1 8 1 4 .3 1 8
Functionality
Note1. Performance not guaranteed
3
ICS9150-08
General I2C serial interface information
A. For the clock generator to be addressed by an I2C controller, the following address must be sent as a start sequence, with an acknoledge bit between each byte.
Clock Generator Address (7 bits)
A(6:0) & R/W# D2(H)
B.
ACK
+ 8 bits dummy command code
ACK
+ 8 bits dummy Byte count
ACK
Then Byte 0, 1, 2, etc in sequence until STOP.
The clock generator is a slave/receiver I2C component. It can read back the data stored in the latches for verification. (set R/W# to 1 above) Read-Back will support Intel PIIX4 "Block-Read" protocol, with a "Byte count" following the address with R/W#=1, then proceding to Byte 0, 1, 2, ...until STOP.
Clock Generator Address (7 bits) Byte Count Readback
A(6:0) & R/W# D3(H)
C. D. E. F.
ACK
ACK
Then Byte 0, 1, 2, etc. in sequence until STOP.
The data transfer rate supported by this clock generator is 100K bits/sec (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition. Byte 0 defaults to a 0, Bytes 1 through 5 default to a 1 (Enabled output state).
G ..
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit Bit 7 Description 0 - 0.25% Spread Spectrum Modulation 1 - 0.5% Spread Spectrum Modulation Bit6 Bit5 Bit4 CPU clock PCI 33.3 (CPU/3) 111 100.2 33.3 (CPU/4) 2 110 133.3 2 37.3 (CPU/3) 2 101 112.0 2 103 34.3 (CPU/3) 100 011 66.8 33.4 (CPU/2) 010 83.3 41.65(CPU/2) 001 75 37.5 (CPU/2) 000 50 25 (CPU/2) 0 - Frequency is selected by hardware select, Latched Inputs 1 - Frequency is selected by Bit 6:4 (above) 0 - Spread Spectrum center spread type. 1 - Spread Spectrum down spread type. 0 - Normal 1 - Spread Spectrum Enabled 0 - Running 1- Tristate all outputs PWD 0
Note1. Default at Power-up will be for latched logic inputs to define frequency. Bits 4, 5, 6 are default to 000, and if bit 3 is written to a 1 to use Bits 6:4, then these should be defined to desired frequency at same write cycle. Note2. Performance not guaranteed
Bit 6:4
Note1
Bit 3 Bit 2 Bit 1 Bit 0
0 0 0 0
Note: PWD = Power-Up Default
I2C is a trademark of Philips Corporation
4
ICS9150-08
Byte 1: CPU, Active/Inactive Register (1= enable, 0 = disable) Byte 2: PCI, Active/Inactive Register (1= enable, 0 = disable)
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# PWD DESCRIPTION 1 Reserved 1 Reserved 1 Reserved 1 Reserved 46 1 SDRAM16 (Act/Inact) 49 1 CPUCLK2 (Act/Inact) 51 1 CPUCLK1 (Act/Inact) 52 1 CPUCLK0 (Act/Inact)
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# PWD DESCRIPTION 1 Reserved 8 1 PCICLKF (Act/Inact) 16 1 PCICLK5 (Act/Inact) 14 1 PCICLK4 (Act/Inact) 13 1 PCICLK3 (Act/Inact) 12 1 PCICLK2 (Act/Inact) 11 1 PCICLK1 (Act/Inact) 9 1 PCICLK0 (Act/Inact)
Byte 3: SDRAM, Active/Inactive Register (1= enable, 0 = disable)
Byte 4: Reserved , Active/Inactive Register (1= enable, 0 = disable)
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# PWD DESCRIPTION 1 Reserved 1 Reserved 30 1 48MHz (Act/Inact) 29 1 24MHz (Act/Inact) 33, 32, 1 SDRAM(12:15) (Act/Inact) 25, 24 22, 21, 1 SDRAM (8:11) (Act/Inact) 19, 18 39, 38, 1 SDRAM (4:7) (Act/Inact) 36, 35 44, 43, 1 SDRAM0 (0:3) (Act/Inact) 41, 40
BIT PIN# PWD DESCRIPTION Bit 7 Latched FS0# Bit 6 1 Reserved Bit 5 1 Reserved Bit 4 Latched FS1# Bit 3 1 Reserved Bit 2 1 Reserved Bit 1 1 Reserved Bit 0 1 Reserved
Byte 5: Peripheral , Active/Inactive Register (1= enable, 0 = disable)
Notes:
BIT PIN# PWD DESCRIPTION Bit 7 1 Reserved Bit 6 Latched FS2# Bit 5 54 1 IOAPIC1 (Act/Inact) Bit 4 55 1 IOAPIC0 (Act/Inact) Bit 3 1 Reserved Bit 2 1 Reserved Bit 1 2 1 REF1 (Act/Inact) Bit 0 3 1 REF0 (Act/Inact)
1. Inactive means outputs are held LOW and are disabled from switching. 2. Latched Frequency Selects (FS#) will be inferted logic load of the input frequency select pin conditions.
5
ICS9150-08
CPU_STOP# Timing Diagram
CPUSTOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation. CPU_STOP# is synchronized by the ICS9150-08. All other clocks will continue to run while the CPUCLKs are disabled. The CPUCLKs will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPUCLK on latency is less than 4 CPUCLKs and CPUCLK off latency is less than 4 CPUCLKs.
Notes: 1. All timing is referenced to the internal CPUCLK. 2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPUCLKs inside the ICS9150-08. 3. All other clocks continue to run undisturbed. 4. PCI_STOP# is shown in a high (true) state.
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9150-08. It is used to turn off the PCICLK (0:5) clocks for low power operation. PCI_STOP# is synchronized by the ICS9150-08 internally. PCICLK (0:5) clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
CPUCLK (Internal)
PCICLK (Internal) PCICLK (Free-running) CPU_STOP#
PCI_STOP#
PCICLK (0:5) (External)
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the device.) 2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized inside the device. 3. All other clocks continue to run undisturbed. 4. CPU_STOP# is shown in a high (true) state.
6
ICS9150-08
Shared Pin Operation Input/Output Pins
Pins 8, 29, 30, 54 on the ICS9150-08 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 4-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm(10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figs. 1 and 2 show the recommended means of implementing this function. In Fig. 1 either one of the resistors is loaded onto the board (selective stuffing) to configure the devices internal logic. Figs. 2a and b provide a single resistor loading option where either solder spot tabs or a physical jumper header may be used. These figures illustrate the optimal PCB physical layout options. These configuration resistors are of such a large ohmic value that they do not effect the low impedance clock signals. The layouts have been optimized to provide as little impedance transition to the clock signal as possible, as it passes through the programming resistor pad(s).
Fig. 1
7
ICS9150-08
Fig. 2a
Fig. 2b
8
ICS9150-08
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . . . . Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . 7.0 V GND 0.5 V to V DD +0.5 V 0C to +70C 115C 65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% (unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Supply Current Input frequency Input Capacitance1 Transition Time1 Clk Stabilization Skew1
1 1
SYMBOL VIH VIL IDD IDDL Fi CIN CINX Ttrans TSTAB TCPU-BUS
CONDITIONS
MIN 2 VSS-0.3
CL = 0 pF; Select @ 66M VDD = 3.3 V; Logic Inputs X1 & X2 pins To 1st crossing of target Freq. From VDD = 3.3 V to 1% target Freq. VT = 1.5 V; 1.0
27
MAX UNITS VDD+0.3 V 0.8 V 100 180 mA 6.0 30 mA 14.318 MHz 5 pF 36 45 ps 1.5 2.6 3 3 4.0 ms ms ns
TYP
Guarenteed by design, not 100% tested in production.
9
ICS9150-08
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = 3.3 V +/-5%; VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew (Window) SYMBOL RDSP2A1 RDSN2A1 VOH2B VOL2B IOH2B IOL2B tr2A1 tf2A1 dt2A1 tsk2A1 VO = VDD*(0.5) VO = VDD*(0.5) IOH = -12.0 mA IOL = 12 mA VOH = 1.7 V VOL = 0.7 V VOL = 0.4 V, VOH = 2.0 V @ 66MHz VOH = 2.0 V, VOL = 0.4 V @ 66MHz VT = 1.25 V 45.0 9.75 9.75 -250 CONDITIONS MIN 10 10 2 2.3 0.2 -30 37 1.3 1.1 51.0 40 10 10 120 100 150 TYP MAX UNITS 20 20 0.4 -19 1.6 1.6 55.0 250 10.25 10.35 350 +250 250 V V mA mA ns ns % ps ns ns ps ps ps
25
VT = 1.25 V period(norm) VT = 1.25 V; 100MHz period(spr) VT = 1.25 V; 100MHz tj1s2A1 tjabs2A1 VT = 1.25 V VT = 1.25 V VT = 1.25 V Dev run avg
Jitter
1
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 30 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
SYMBOL RDSP1 1 RDSN1 VOH1 VOL1 IOH1 IOL1 tr1 tf1
1 1 1 1
CONDITIONS VO = VDD*(0.5) VO = VDD*(0.5) IOH = -28 mA IOL = 23 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.8 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.8 V VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 12 12 2.4
TYP 23 20 2.9 0.2 -58 52 1.5 1.4
MAX 55 55 0.4 -22 2.0 2.0 55.0 250 150 500
UNITS V V mA mA ns ns % ps ps ps
25
dt1
45.0
50.0 80 50 200
tsk11 tj1s1 tjabs11
1
Guarenteed by design, not 100% tested in production.
10
ICS9150-08
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD =VDDL 3.3 V +/-5%; CL = 30 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew ( output to output ) Skew Propagation Delay ( Bufferin to output )
1
SYMBOL RDSP2A1 RDSN2A1 VOH2A VOL2A IOH2A IOL2A tr2A1 tf2A1 dt2A1 tsk2A1 tsk2A1
CONDITIONS VO = VDD*(0.5) VO = VDD*(0.5) IOH = -28 mA IOL = 19 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.8 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.8 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 10 10 2.4
TYP
33
41
3 0.3 -72 55 1.6 1.2 46 200 4.5
MAX UNITS 20 20 V 0.4 V -42 mA mA 2.0 ns 2.0 ns 51 % 600 ps 55 ns
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - 24M, 48M, REF 1
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Jitter
1
SYMBOL RDSP5
1 1
CONDITIONS VO = VDD*(0.5) VO = VDD*(0.5) IOH = -8 mA IOL = 8 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.8 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.8 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN
TYP 20 55 2.9 0.18 -42 26 1.2 2.0
MAX UNITS 60 100 0.4 -14 2.0 2.4 60.0 2.1 3.5 W W V V mA mA ns ns % ns ns
RDSN5 VOH5 VOL5 IOH5 IOL5 tr5 tf5
1 1 1 1
2.4
16
dt5
40.0
54.0 100 0.35
tj1s5
tjabs5
1
Guarenteed by design, not 100% tested in production.
11
ICS9150-08
Electrical Characteristics - IOAPIC
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Jitter
1
SYMBOL RDSP5
1 1
CONDITIONS VO = VDD*(0.5) VO = VDD*(0.5) IOH = -8 mA IOL = 1.2 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.8 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.8 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN
TYP 20 55 2.9 0.2 -42 27 2.0 2.8
MAX UNITS 60 100 0.4 -14 2.6 3.2 58.0 250 800 W W V V mA mA ns ns % ns ps
RDSN5 VOH5 VOL5 IOH5 IOL5 tr5 tf5
1 1 1 1
2.4
10
dt5
48.0
54.0 100 550
tj1s5
tjabs5
1
Guarenteed by design, not 100% tested in production.
12
ICS9150-08
SSOP Package
SYMBOL A A1 A2 B C D E e H h L N
X
COMMON DIMENSIONS MIN. NOM. MAX. .095 .101 .110 .008 .012 .016 .088 .090 .092 .008 .010 .0135 .005 .010 See Variations .292 .296 .299 0.025 BSC .400 .406 .410 .010 .013 .016 .024 .032 .040 See Variations 0 5 8 .085 .093 .100
VARIATIONS AC AD MIN. .620 .720
D NOM. .625 .725
N MAX. .630 .730 48 56
Ordering Information
ICS9150F-08
Example:
ICS XXXX F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
13
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

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